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? semiconductor components industries, llc, 2017 december, 2017 ? rev. p1 1 publication order number: ncp11367/d ncp11367 product preview high voltage primary side pwm switcher for low power offline smps description the ncp11367 offers a new integrated fet solution targeting output power levels up to 12 w continuously in a universal ? mains flyback application. thanks to a novel method this new controller saves the secondary feedback circuitry for constant voltage and constant current regulation, achieving excellent line and load regulation without traditional opto coupler and tl431 voltage reference. the ncp11367 operates in valley lockout quasi ? resonant peak current mode control mode at high load to provide high efficiency. when the power on the secondary side starts to diminish, the controller automatically adjusts the duty ? cycle then at lower load the controller enters in pulse frequency modulation at fixed peak current with a valley switching detection. this technique allows keeping the output regulation with tiny dummy load. valley lockout at the first 4 valleys prevent valley jumping operation and then a valley switching at lower load provides high efficiency. features ? integrated 650 v power mosfet with r ds(on) of 3.2 typical @ 25 c ? constant voltage primary ? side regulation < 5% ? internal line feedforward ? quasi ? resonant with v alley switching operation ? optimized light load efficiency and stand ? by performance ? frequency clamp options ? cycle by cycle peak current limit ? output voltage under voltage and over voltage protection (uvp or ovp) ? secondary diode or winding short ? circuit protection ? uvp built ? in blanking time to support 5000 f capacitive load capability ? cable drop compensation adjustment ? wide operation v cc range (up to 28 v) ? low start ? up current ? cs & vs/zcd pin short and open protection ? internal temperature shutdown ? internal and fixed frequency jittering for better emi signature typical applications ? low power ac/dc adapters for routers and set ? top box this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. www. onsemi.com tssop20 case 948bl pin assignment 1 2 18 20 19 3 17 4 16 5 6 7 8 9 10 13 15 14 12 11 nc gnd nc drain drain src cs v s / zcd comp gnd drain drain nc vcc marking diagram xxxx xxxx alyw xxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) see detailed ordering and shipping information on page 23 of this data sheet. ordering information
ncp11367 www. onsemi.com 2 rtn_out 0 ac ac out 0 ncp11367 gnd 1 comp 2 nc 3 vs/zcd 4 cs 5 src 6 drain 10 drain 11 nc 15 gnd 16 vcc 17 nc 20 drain 9 drain 12 0 1 2 3 4 5 figure 1. ncp11367 application schematic diagram
ncp11367 www. onsemi.com 3 vcc and logic management of double hiccup s r q uvlo gnd src uvlo poreset v dd v cc(ovp) fb reset max_ipk reset soft start poreset vs / zcd ocp timer count reset timer v cc(reset) reset double_hiccup_ends comp v cc clamp leb1 blanking cs v ilim ota ss qr multi ? mode valley lockout & valley switching & vco management poreset 126% v ref_cv2 i cs v dd poreset dblehiccup v uvp ovp_cmp uvp_cmp leb2 v cs(stop) 4 clk counter reset counter note: ovp: over voltage protection uvp: under voltage protection ocp: over current protection scp: short circuit protection cbc: cable compensation t leb1 > t leb2 ocp s r q peak current control 1/k comp dblehiccup v cc(ovp) cs pin open (v cs > 1.2 v) & short (v cs < 50 mv) detection is activated at each startup i cs_en i cs_en scp cs pin fault v ref_cv2 drain s r q uvp v cc en_uvp en_uvp uvp zero crossing & signal sampling cc control sampled v out fb cbc fb_cc fb_cv v ref_cv1 4 clk counter dblehiccup v ref_cc control law & primary peak current control ovp ss v jitter v dd cbc_gain scp figure 2. functional block diagram
ncp11367 www. onsemi.com 4 table 1. pin function description pin out ncp11367 name function 1 gnd ground reference. 2 comp this is the error amplifier output. the network connected between this pin and the ground adjusts the regulation loop bandwidth. 3, 15, 20 nc not connected 4 v s /zcd connected to the auxiliary winding; this pin senses the voltage output for the primary regulation and detects the core reset event for the quasi ? resonant mode of operation. 5 cs this pin monitors the primary peak current. 6 src this pin is the source pin of the integrated power mosfet. 9,10,11,12 drain these pins are all connected to the drain of the power mosfet. large cooper area must be layouted around these pins in order to improve the losses dissipation. 7,8,13,14,18,19 ? these pins are cut to keep creepage distance between high voltage pin and low voltage pin 16 gnd ground reference. 17 v cc this pin is connected to an external auxiliary voltage and supplies the controller. table 2. maximum ratings symbol rating value unit v cc(max) i cc(max) maximum power supply voltage, vcc pin, continuous voltage maximum current for vcc pin ? 0.3 to 28 internally limited v ma v cc / t maximum slew rate on v cc pin during startup phase +0.4 v/ s bv dss drain voltage to source ? 0.3 to 650 v i d(max) drain current continuous, t j = 25 c 3 a e as single pulse avalanche rating 120 mj v max i max maximum voltage on low power pins (except pins drain and vcc) current range for low power pins (except pins drain and vcc) ? 0.3, 5.5 ? 2, +5 v ma r j ? a thermal resistance junction ? to ? air, 2.0 oz printed circuit copper clad 0.36 sq. inch 1.0 sq. inch 112 94 c/w t j(max) maximum junction temperature for both controller and power mosfet dice 150 c operating temperature range ? 40 to +125 c storage temperature range ? 60 to +150 c human body model esd capability per jedec jesd22 ? a114f 2 kv machine model esd capability (all pins except drv) per jedec jesd22 ? a115c 200 v charged ? device model esd capability per jedec jesd22 ? c101e 500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device contains latch/up protection and exceeds 100 ma per jedec standard jesd78.
ncp11367 www. onsemi.com 5 table 3. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max tj = 150 c, unless otherwise noted) characteristics condition symbol min typ max unit power switch circuit power switch circuit & startup breakdown voltage i d(off) = 250 a, t j = 25 c bv dss 650 ? ? v power switch circuit on ? state resistance i d = 0.5 a t j = 25 c t j = 125 c r ds(on) ? ? 3.2 6.5 3.8 7.4 power switch circuit & startup breakdown voltage off ? state leakage current t j = 125 c (v ds = 650 v) i dss(off) ? ? 2.5 a switching characteristics r l = 50 , v ds set for i d = 0.5 a t on t off ? ? 20 10 ? ? ns supply section and v cc management v cc level at which driving pulses are authorized v cc increasing v cc(on) 16 18 20 v v cc level at which driving pulses are stopped v cc decreasing v cc(off) 6.0 6.5 7.0 v internal latch / logic reset level v cc(reset) ? 6.25 ? v internal autorecovery reset level (note 4) v cc(reset_auto) 0.6 ? ? v hysteresis above v cc(off) for fast hiccup in latch mode v cc(latch_hyst) ? 0.2 ? v hysteresis below v cc(off) before latch reset v cc(reset_hyst) 0.15 0.25 0.45 v over voltage protection over voltage threshold v cc(ovp) 24 26 28 v start ? up supply current, controller disabled or latched v cc < v cc(on) & v cc increasing from 0 v i cc(start) ? 3.6 5.5 a internal ic consumption, steady state f sw = 65 khz i cc(steady) ? 1.6 1.8 ma internal ic consumption in minimum frequency clamp vco mode, f sw = f vco(min) , v comp = gnd f vco(min) = 1 khz f vco(min) = 200 hz i cc(vco) ? ? 325 210 430 370 internal ic consumption in fault mode (after a fault when v cc decreasing to v cc(off) ) autorecovery mode i cc(auto) ? 2.0 2.2 ma internal ic consumption in fault mode (after a fault when v cc decreasing to v cc(off) ) latch mode i cc(latch) ? 1.0 1.2 ma current comparator current sense voltage threshold v comp = v comp(max) , v cs increasing v ilim 0.76 0.8 0.84 v cycle by cycle leading edge blanking duration t leb1 260 320 380 ns cycle by cycle current sense propagation delay v cs > (v ilim + 100 mv) to drv turn ? off t ilim ? 50 100 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions. 3. the value is not subjected to production test, verified by design and characterization. the thermal shutdown temperature refe rs to the junction temperature of the controller in order to keep the junction temperature of the power mosfet below its maximum rating j unction temperature. thermal shut down level will be adjusted after the silicon evaluation. 4. guaranteed by design.
ncp11367 www. onsemi.com 6 table 3. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max tj = 150 c, unless otherwise noted) characteristics unit max typ min symbol condition current comparator timer delay before detecting an overload condition when cs pin v ilim (note 2) t ocp 50 70 90 ms threshold for immediate fault protection activation v cs(stop) 1.08 1.2 1.32 v leading edge blanking duration for v cs(stop) t leb2 ? 120 ? ns maximum peak current level at which vco takes over or frozen peak current v cs increasing 0.6 v < v comp < 1.9 v (other possible options on demand) v vcs(vco) ? 250 ? mv minimum peak current level vcs increasing vcomp < 0.2 v (other possible options on demand) v cs(stb) ? 65 ? mv regulation block internal voltage reference for constant current regulation t j = 25 c ? 40 c< t j < 125 c v ref_cc 0.98 0.97 1.00 1.00 1.02 1.03 v internal voltage reference for constant voltage regulation t j = 25 c ? 40 c< t j < 125 c v ref_cv1 2.450 2.425 2.500 2.500 2.550 2.575 v internal voltage reference for constant voltage regulation when cable compensation is enabled v out = 5 v v ref_cv2 ? v ref_cv1+ (cbc/2) ? v internal voltage reference for constant voltage regulation when cable compensation is enabled v out = 12 v v ref_cv2 ? v ref_cv1+ (cbc/4.8) ? v error amplifier current capability i ea ? 40 ? a error amplifier gain g ea 150 200 250 s error amplifier output voltage internal offset on comp pin v comp(max) v comp(min) v comp(offset) ? ? ? 4.9 0 1.1 ? ? ? v internal current setpoint division ratio k comp ? 4 ? ? valley thresholds transition from 1 st to 2 nd valley transition from 2 nd to 3 rd valley transition from 3 rd to 4 th valley transition from 4 th valley to vco transition from vco to 4 th valley transition from 4 th to 3 rd valley transition from 3 rd to 2 nd valley transition from 2 nd to 1 st valley v comp decreasing v comp decreasing v comp decreasing v comp decreasing v comp increasing v comp increasing v comp increasing v comp increasing v h2d v h3d v h4d v hvcod v hvcoi v h4i v h3i v h2i ? ? ? ? ? ? ? ? 2.50 2.30 2.10 1.90 2.50 2.70 2.90 3.10 ? ? ? ? ? ? ? ? v minimal difference between any two valleys v comp increasing or v comp decreasing v h 176 ? ? mv internal dead time generation for vco mode entering in vco when v comp is decreasing and crosses v hvcod t dt(start) ? 1.15 ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions. 3. the value is not subjected to production test, verified by design and characterization. the thermal shutdown temperature refe rs to the junction temperature of the controller in order to keep the junction temperature of the power mosfet below its maximum rating j unction temperature. thermal shut down level will be adjusted after the silicon evaluation. 4. guaranteed by design.
ncp11367 www. onsemi.com 7 table 3. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max tj = 150 c, unless otherwise noted) characteristics unit max typ min symbol condition regulation block internal dead time generation for vco mode leaving vco mode when v comp is increasing and crosses v hvcoi t dt(ends) ? 650 ? ns internal dead time generation for vco mode when in vco mode ? 1 ? khz option v comp = 1.8 v v comp = 1.4 v v comp = 0.9 v v comp < 0.2 v t dt ? ? ? ? 1.6 11 110 1000 ? ? ? ? s minimum operating frequency in vco mode v comp = gnd option 1 option 2 (other possible options on demand) f vco(min) 0.8 0.16 1.0 0.200 1.2 0.24 khz maximum operating frequency option 1 option 2 option 3 option 4 f max ? 72 99 127 no clamp 80 110 140 ? 88 121 153 khz maximum on time t on(max) 32 36 40 s demagnetization input ? zero voltage detection circuit and voltage sense v zcd threshold voltage v zcd decreasing v zcd(th) 25 45 65 mv v zcd hysteresis v zcd increasing v zcd(hys) 15 30 45 mv threshold voltage for output short circuit or aux. winding short circuit detection after t blank_pd if v zcd < v zcd(short) v zcd(short) 30 50 70 mv delay after on ? time that the v s / zcd is still pulled to ground when v comp > 1.7 v when v comp < 1.7 v t short_zcd ? ? 0.750 0.350 ? ? s blanking delay after on ? time (v s /zcd pin is disconnected from the internal circuitry) when v comp > 1.7 v when v comp < 1.7 v t blank_zcd ? ? 1.450 0.750 ? ? s timeout after last demagnetization transition t out 4.0 4.5 5.0 s input leakage current v cc > v cc(on) v zcd = 4 v, drv is low i zcd ? ? 0.1 a delay from valley detection to drain low t zcd_delay ? 290 ? ns soft start internal fixed soft start duration current sense peak current rising from v cs(vco) to v ilim t ss 3 4 5 ms jittering frequency of the jittering cs pin source current option 1 (other possible options on demand) f jitter 1.2 1.5 1.8 khz product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions. 3. the value is not subjected to production test, verified by design and characterization. the thermal shutdown temperature refe rs to the junction temperature of the controller in order to keep the junction temperature of the power mosfet below its maximum rating j unction temperature. thermal shut down level will be adjusted after the silicon evaluation. 4. guaranteed by design.
ncp11367 www. onsemi.com 8 table 3. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max tj = 150 c, unless otherwise noted) characteristics unit max typ min symbol condition jittering peak jitter voltage added to pwm comparator option 1 (other possible options on demand) v jitter 45 60 75 mv line feed forward line feed forward compensation gain k lff ? 300 ? a/v fault protection controller thermal shutdown device switching (f sw ~ 65 khz) ? t j rising (note 3) t shtdn(on) ? 130 ? c thermal shutdown hysteresis device switching (f sw ~ 65 khz) ? t j falling t shtdn(off) ? 100 ? c number of drive cycle before triggering short circuit protection v comp = v comp(max) , v cs > v cs(stop) or internal sampled v out > v ovp (note 4) t _count ? 4 ? ? fault level detection for ovp internal sampled v out increasing v ovp = v ref_cv2 +26% v ovp 2.95 3.15 3.35 v fault level detection for uvp double hiccup autorecovery (uvp detection is disabled during t en_uvp ) internal sampled v out de- creasing v uvp 1.40 1.50 1.60 v blanking time for uvp detection starting after the soft start option 1 ? 5000 f capaci- tive loading (other possible options on demand) t en_uvp ? 76 ? ms pull ? up current source on cs pin for open or short circuit detection when v cs > v cs_min i cs ? 60 ? a cs pin open detection cs pin open v cs(open) ? 1.2 ? v cs pin short detection v cs_min ? 50 70 mv cs pin short detection timer (note 4) t cs_short ? 3 ? s cable drop compensation offset applied on v ref_cv1 at the maximum constant current valid for 12 v output only option a option b option c option d cbc ? ? ? ? none 200 250 300 ? ? ? ? mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. the timer can be reset if there are 4 drv cycles without overload or short circuit conditions. 3. the value is not subjected to production test, verified by design and characterization. the thermal shutdown temperature refe rs to the junction temperature of the controller in order to keep the junction temperature of the power mosfet below its maximum rating j unction temperature. thermal shut down level will be adjusted after the silicon evaluation. 4. guaranteed by design.
ncp11367 www. onsemi.com 9 typical characteristics 630 650 670 690 710 730 750 770 790 -50 -25 0 25 50 75 100 125 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 -50 -25 0 25 50 75 100 125 17.88 17.93 17.98 18.03 18.08 -50 -25 0 25 50 75 100 125 6.526 6.531 6.536 6.541 6.546 6.551 6.556 6.561 6.566 -50 -25 0 25 50 75 100 125 2.4 2.9 3.4 3.9 4.4 4.9 -50 -25 0 25 50 75 100 125 figure 3. bv dss vs. junction temperature figure 4. r ds(on) vs. junction temperature figure 5. v cc(on) vs. junction temperature figure 6. v cc(off) vs. junction temperature figure 7. v cc(reset) vs. junction temperature figure 8. i cc(start) vs. junction temperature temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) bv dss (v) r ds(on) ( ) v cc(on) (v) v cc(off) (v) v cc(reset) (v) i cc(start) ( a) -50 -25 0 25 50 75 100 125 6.236 6.241 6.246 6.251 6.256 6.261 6.266 6.271 6.276
ncp11367 www. onsemi.com 10 typical characteristics (continued) 0.797 0.799 0.801 0.803 0.805 0.807 -50 -25 0 25 50 75 100 125 322 322.5 323 323.5 324 324.5 325 325.5 326 326.5 327 -50 -25 0 25 50 75 100 125 42 47 52 57 62 -50 -25 0 25 50 75 100 125 1.193 1.195 1.197 1.199 1.201 1.203 1.205 1.207 -50 -25 0 25 50 75 100 125 247 248 249 250 251 252 253 -50 -25 0 25 50 75 100 125 67.6 67.65 67.7 67.75 67.8 67.85 67.9 67.95 68 -50 -25 0 25 50 75 100 125 figure 9. v ilim vs. junction temperature temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) figure 10. t lebi vs. junction temperature figure 11. t ilim vs. junction temperature figure 12. v cs(stop) vs. junction temperature figure 13. v cs(vco) vs. junction temperature figure 14. v cs(stb) vs. junction temperature v ilim (v) t leb1 (ns) v cs(stop) (v) t ilim (ns) v cs(vco) (mv ) v cs(stb) (mv )
ncp11367 www. onsemi.com 11 typical characteristics (continued) 0.997 0.999 1.001 1.003 1.005 1.007 1.009 -50 -25 0 25 50 75 100 125 43.5 44 44.5 45 45.5 46 46.5 47 47.5 48 48.5 -50 -25 0 25 50 75 100 125 52 52.5 53 53.5 54 54.5 55 -50 -25 0 25 50 75 100 125 1.486 1.491 1.496 1.501 1.506 -50 -25 0 25 50 75 100 125 temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) temperature ( c) figure 15. v ref_cc vs. junction temperature figure 16. v ref_cvi vs. junction temperature figure 17. v zcd(th) vs. junction temperature figure 18. v zcd(short) vs. junction temperature figure 19. v ovp vs. junction temperature figure 20. v uvp vs. junction temperature v ref_cc (v) v ref_cv1 (v) v zcd(th) (mv) v zcd(short) (mv) v ovp (v) v uvp (v) -50 -25 0 25 50 75 100 125 2.48 2.485 2.49 2.495 2.5 2.505 2.51 -50 -25 0 25 50 75 100 125 -50 3.138 3.143 3.148 3.153 3.158 3.163 3.168 3.173
ncp11367 www. onsemi.com 12 typical characteristics (continued) 76.3 76.4 76.5 76.6 76.7 76.8 76.9 77 77.1 77.2 -50 -25 0 25 50 75 100 125 temperature ( c) figure 21. t en_uvp vs. junction temperature t en_uvp (ms) table 4. fault mode states table event timer protection next device status release to normal operation mode overcurrent v cs > v ilim ocp timer double hiccup ? resume to normal operation: if 4 pulses from fb reset & then reset timer ? resume operation after double hiccup winding short v cs > v cs(stop) 4 consecutive pulses with v cs > v cs(stop) double hiccup resume operation after double hiccup cs pin fault: short & open before start ? up immediate double hiccup resume operation after double hiccup zcd short v zcd < v zcd(short) after t blank_zcd time 4 consecutive pulses double hiccup resume operation after double hiccup low supply v cc < v cc(off) 10 ? s timer simple hiccup resume operation after double hiccup high supply v cc > v cc(ovp) 10 ? s timer double hiccup resume operation after double hiccup internal v out ovp: v out > 126% v ref_cv2 4 consecutive pulses double hiccup resume operation after double hiccup internal v out uvp: v out < 60% v ref_cv2 , when v out is decreasing only 4 consecutive pulses double hiccup resume operation after double hiccup internal tsd 10 ? s timer double hiccup resume operation after double hiccup & t < (t shtdn(off) )
ncp11367 www. onsemi.com 13 application information the ncp11367 is a flyback power supply switcher providing a means to implement primary side constant ? current regulation and secondary side constant ? voltage regulation. ncp11367 implements a current ? mode architecture operating in quasi ? resonant mode. the controller prevents valley ? jumping instability and steadily locks out in a selected valley as the power demand goes down. as long as the controller is able to detect a valley, the new cycle or the following drive remains in a valley. thanks to a dedicated valley detection circuitry operating at any line and load conditions, the power supply efficiency will always be optimized. in order to prevent any high switching frequency two frequency clamp options are available. ? quasi ? resonance current ? mode operation : implementing quasi ? resonance operation in peak current ? mode control optimizes the efficiency by switching in the valley of the mosfet drain ? source voltage. thanks to a proprietary circuitry, the controller locks ? out in a selected valley and remains locked until the input voltage significantly changes. only the four first valleys could be locked out. when the load current diminishes, valley switching mode of operation is kept but without valley lock ? out. valley ? switching operation across the entire input/output conditions brings efficiency improvement and lets the designer build higher ? density converters. ? frequency clamp : as the frequency is not fixed and dependent on the line, load and transformer specifications, it is important to prevent switching frequency runaway for applications requiring maximum switching frequencies up to 90 khz or 130 khz. three frequency clamp options at 80 khz, 110 khz or 140 khz are available for this purpose. in case frequency clamp is not needed, a specific version of the ncp11367 exists in which the clamp is deactivated. figure 22. constant-voltage & constant-current mode cv mode cc mode 0 v nom v out i nom i out ? primary side constant current regulation : ncp11367 controls and regulates the output current at a constant level regardless of the input and output voltage conditions. this function offers tight over power protection by estimating and limiting the maximum output current from the primary side, without any particular sensor. ? soft ? start : 4 ? ms internal fixed soft start guarantees a peak current starting from zero to its nominal value with smooth transition in order to prevent any overstress on the power components at each startup. ? cycle ? by ? cycle peak curr ent limit : if the max peak current reaches the v ilim level, the over current protection timer is enabled and starts counting. if the overload lasts t ocp delay, then the fault is detected and the controller stops immediately driving the power mosfet. the controller enters in a double hiccup mode before autorecovering with a new startup cycle. ? v cc over voltage protection : if the v cc voltage reaches the v cc(ovp) threshold the controller enters in fault mode. thus it stops driving pulse on drv pin. the part enters in double hiccup mode before resuming operation. ? winding short ? circuit protection : an additional comparator senses the cs signal and stops the controller if v cs reaches v ilim +50% (after a reduced leb: t leb2 ). short circuit protection is enabled only if 4 consecutive pulses reach scp level. this small counter prevents any false triggering of short circuit protection during surge test for instance. this fault is detected and operations will be resumed like in a case of v cc over voltage protection. ? v out over voltage protection : if the internally ? built output voltage becomes higher than v ovp level (v ref_cv1 + 26%) a fault is detected. this fault is detected and operations are resumed like in the v cc over voltage protection case. ? v out under voltage protection : after each circuit power on sequence, v out uvp detection is enabled only after the startup timer t en_uvp . this timer ensures that the power supply is able to fuel the output capacitor before checking the output voltage in on target. after this startup blanking time, uvp detection is enabled and monitors the output voltage level. when the power supply is running in constant ? current mode and when the output voltage falls below v uvp level, the controller stops sending drive pulses and enters a double hiccup mode before resuming operations. ? v s /zcd pin short protection : at the beginning of each off ? time period, the v s /zcd pin is tested to check whether it is shorted or left open. in case a fault is detected, the controller enters in a double hiccup mode before resuming operations. ? emi jittering : a low ? frequency triangular voltage vaweform is added to the cs pin. this helps spreading out energy in conducted noise analysis. jittering is disabled in frequency foldback mode. ? frequency foldback : in frequency foldback mode, the system reduces the switching frequency by adding
ncp11367 www. onsemi.com 14 some dead ? time after the 4 th valley is detected. the controller will still run in valley switching mode even when the ff is enabled. ? cable drop compensation : the cable drop compensation value (for example 200 mv) will be reached at the maximum constant current value. then the cable compensation is proportional to the output current as illustrated by the following figure. figure 23. cable compensation vs. output current load cable compensation i out 0 i out_cc 0 cbc ? temperature shutdown : if the junction temperature reaches the t shtdn level, the controller stop driving the power mosfet until the junction temperature decreases to t shtdn(off) , then the operation is resumed after a double hiccup mode. detailed application information start ? up sequence the ncp11367 start ? up voltage is made purposely high to permit large energy storage in a small v cc capacitor value. this helps operate with a small start ? up current which, together with a small v cc capacitor, will not hamper the start ? up time. to further reduce the standby power, the start ? up current of the controller is extremely low (see i cc(start) ). the start ? up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation. figure 24. the startup resistor can be connected to the input mains for further power dissipation reduction. input mains aux. winding v cc r start-up c bulk c vcc the first step starts with the calculation of the needed v cc capacitor which will supply the controller when it operates until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 ms and 20 ms. if we consider we need at least an ener gy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: (eq. 1) c vcc i cc t 1 v cc ( on ) v cc ( off ) 1.6m 10m 18 6.5 1.4 f let us select a 1.5 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t 1 . the v cc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 v to the v cc(on) of the ic. this current has to be selected to ensure a start ? up at the lowest mains (85 v rms) to be less than 3 s (2.5 s for design margin): (eq. 2) i charge v cc(on) c vcc t start up 18 1.5 2.5 11 a if we account for the i cc(start) = 6.3 a (maximum) that will flow inside the controller, then the total char ging current delivered by the start ? up resistor must be 17.3 a. if we connect the start ? up network to the mains (half ? wave connection then), we know that the average current flowing into this start ? up resistor will be the smallest when v cc reaches the v cc(on) of the controller:
ncp11367 www. onsemi.com 15 i cvcc,min v ac,rms 2 v cc(on) r start ? up (eq. 3) to make sure this current is always greater than 16 a, then the minimum value for r start ? up can be extracted: r start ? up 85 2 18 17.3 1.17 m (eq. 4) this calculation is purely theoretical, considering a constant charging current. in reality , the take over time can be shorter (or longer!) and it can lead to a reduction of the v cc capacitor. thus, a decrease in charging current and an increase of the start ? up resistor can be experimentally tested, for the benefit of standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter . if we chose the 1.2 ? m resistor as suggested by (eq. 4), the dissipated power at high line amounts to: p r start ? up,max v ac,peak 2 4 r start ? up 230 2
2 4 1.1 m 24 mw (eq. 5) primary side regulation: constant current operation figure 25 portrays idealized primary and secondary transformer currents of a flyback converter operating in discontinuous conduction mode (dcm). i p (t) i s (t), i out i out = < i s(t) > , ppk i t demag t sw time time t on , , ppk spk ps i i n = figure 25. primary and secondary transformer current waveforms when the primary power mosfet is turned on, the primary current is illustrated by the green curve of figure 25. when the power mosfet is turned off the primary side current drops to zero and the current into the secondary winding immediately rises to its peak value equal to the primary peak current divided by the primary to secondary turns ratio. this is an ideal situation in which the leakage inductance action is neglected. the output current delivered to the load is equal to the average value of the secondary winding current, thus we can write: i out ? i sec (t) ? i p,pk 2n ps t demag t sw (eq. 6) where: ? t sw is the switching period ? t demag is the demagnetizing time of the transformer ? n ps is the secondary to primary turns ratio, where n p & n s are respectively the transformer primary and secondary turns: n ps n s n p (eq. 7) ? i p,pk is the magnetizing peak current sensed across the sense resistor on cs pin: i p,pk v cs r sense (eq. 8) internal constant current regulation block is building the constant current feedback information as follow: v fb_cc v ref_cc t sw t demag (eq. 9) as the controller monitors the primary peak current via the sense resistor and due to the internal current setpoint divider ( k comp ) between the cs pin and the internal feedback information, the output current could be written as follow: i out v ref_cc 8n ps r sense (eq. 10) the output current value is set by choosing the sense resistor value: r sense v ref_cc 8n ps i out (eq. 11) primary side regulation: constant voltage operation in primary side constant voltage regulation, the output voltage is sensed via the auxiliary winding. during the on ? time period, the energy is stored in the transformer gap.
ncp11367 www. onsemi.com 16 during the off ? time this energy stored in the transformer is delivered to the secondary and auxiliary windings. as illustrated by figure 26, when the transformer energy is delivered to the secondary, the auxiliary voltage sums the output voltage scaled by the auxiliary and secondary turns ratios and the secondary forward diode voltage. this secondary forward diode voltage could be split in two elements: the first part is the forward voltage of the diode ( v f ), and the second is related to the dynamic resistance of the diode multiplied by secondary current ( r d i s (t) ). where this second term will be dependant of the load and line conditions. pa out ps n v n 0v v aux (t) time t demag t sw time , ppk i time t on i p (t) i s (t), i out i out = < i s(t) > () sec pa out f ps n vvi n + pa in ps n v n ? , , ppk spk ps i i n = figure 26. typical idealized waveforms of a flyback transformer in dcm to reach an accurate primary ? side constant ? voltage regulation, the controller detects the end of the demagnetization time and precisely samples output voltage level seen on the auxiliary winding. as this moment coincides with the secondary ? side current equal to zero, the diode forward voltage drop becomes independent from the loading conditions. thus when the secondary current i s (t) reaches zero ampere, the auxiliary is sensed: v aux v out n pa n ps (eq. 12) where: n pa is the auxiliary to primary turns ratio, where n p & n a are respectively the primary and auxiliary turns: n pa n a n p (eq. 13) figure 27 illustrates how the constant voltage feedback has been built. the auxiliary winding voltage must be scaled down via the resistor divider to v ref_cv1 level before building the constant voltage feedback error. v ref_cv1 r s2 r s1 r s2 v aux (eq. 14) by inserting (eq. 12) into (eq. 14) we obtain the following equation: v ref_cv1 r s2 r s1 r s2 n pa n ps v out (eq. 15) once the sampled v out is applied to the negative input terminal of the operational transconductance amplifier (ota) and compared to the internal voltage reference an adequate voltage feedback is built. the ota output being pinned out, it is possible to compensate the converter and adjust step load response to what the project requires.
ncp11367 www. onsemi.com 17 vs / zcd comp ota zero crossing & signal sampling sampled v out fb_cv auxiliary r s1 r s2 v ref_cv1 r1 c1 c2 t short_zcd t figure 27. constant voltage feedback arrangement blank_zcd when the power mosfet is released at the end of the on time, because of the transformer leakage inductance and the drain lumped capacitance some voltage ringing appears on the drain node. these voltage ringings are also visible on the auxiliary winding and could cheat the controller detection circuits. to avoid false detection operations, two protecting circuits have been implemented on the v s /zcd pin (see figure 28): 1. an internal switch grounds the v s /zcd pin during t on +t short_zcd in order to protect the pin from negative voltage. 2. in order to prevent any misdetection from the zero crossing block an internal switch disconnects v s /zcd pin until t blank_zcd time ends. figure 28. v s /zcd pin waveforms constant ? current and constant ? voltage overall regulation as already presented in the two previous paragraphs, the controller integrates two different feedback loops: the first one deals with the constant ? current regulation scheme while the second one builds the constant ? voltage regulation with an opto ? based voltage loop. one of the two feedback paths sets the primary peak current into the transformer. during startup phase, however, the peak current is controlled by the softstart. zero current detection the ncp11367 integrates a quasi ? resonant (qr) flyback controller. the power switch turn ? off of a qr converter is determined by the peak current whose value depends on the feedback loop. the switch restart event is determined by the transformer demagnetization end. the demagnetization end is detected by monitoring the transformer auxiliary winding voltage. turning on the power switch once the transformer is demagnetized (or reset) reduces turn ? on switching losses. once the transformer is demagnetized, the drain voltage
ncp11367 www. onsemi.com 18 starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lumped capacitance, eventually settling at the input voltage value. a qr controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or ?valley? to reduce turn ? on switching losses and electromagnetic interference (emi). as sketched by figure 29, a valley is detected once the zcd pin voltage falls below the qr flyback demagnetization threshold, v zcd(th) , typically 45 mv. the controller will switch once the valley is detected or increment the valley counter depending on fb voltage. r s1 r s2 zcd timeout ? t out qr multi ? mode valley lockout & valley switching & vco management blanking t blank_zcd s r q drv (internal) v zcd(th) figure 29. valley lockout detection circuitry internal schematic timeout the zcd block actually detects falling edges of the auxiliary winding voltage applied to the zcd pin. at start ? up or during other transient phases, the zcd comparator may be unable to detect such an event. also, in the case of extremely damped oscillations, the system may not succeed in detecting all the valleys required by valley lockout operation (vlo, see next section). in this condition, the ncp11367 ensures continued operation by incorporating a maximum timeout period that resets itself when a demagnetization phase is properly detected. in case the ringing signal is too weak or heavily damped, the timeout signal supersedes the zcd signal for the valley counter. figure 10 shows the timeout period generator circuit schematic. the timeout duration, t out , is set to 4.5 s (typ.). in vlo operation, the timeout occurrences are counted instead of valleys when the drain ? source voltage oscillations are too damped to be detected. for instance, assume the circuit must turn on at the third valley and the zcd ringing only enables the detection of: ? valleys #1 to #2: the circuit generates a drv pulse t out (steady ? state timeout delay) after valley #2 detection. ? valley #1: the timeout delay must run twice so that the circuit generates a drv pulse 9 s (2* t out typ.) after valley #1 detection. valley lockout (vlo) and frequency foldback (ff) the operating frequency of a traditional quasi ? resonant (qr) flyback controller is inversely proportional to the system load. in other words, a load reduction increases the operating frequency. a maximum frequency clamp can be useful to limit the operating frequency range. however, when associated with a valley ? switching circuit, instabilities can arise because of the discrete frequency jumps. the controller tends to hesitate between two valleys and audible noise can be generated to avoid this issue, the ncp11367 incorporates a proprietary valley lockout circuitry which prevents so ? called valley jumping. once a valley is selected, the controller stays locked in this valley until the input level or output power chan ges significantly. this technique extends qr operation over a wider output power range while maintaining good efficiency and naturally limiting the maximum operating frequency. the operating valley (from 1 st to 4 th valley) is determined by the internal feedback level (internal fb node on figure 2). as fb voltage level decreases or increases, the valley comparators toggle one after another to select the proper valley. the decimal counter increases each time a valley is detected. the activation of an ?n? valley comparator blanks the ?n ? 1? or ?n+1? valley comparator output depending if v fb decreases or increases, respectively. figure 30 shows a typical frequency characteristic obtained at low line in a 10 ? w charger.
ncp11367 www. onsemi.com 19 0 1 2 3 4 5 6 7 8 910 0 fsw versus pout at vinlow pout (w) fsw (hz) 1 st 2 nd 3 rd 4 th 5 th frequency foldback mode 1 st 2 nd 3 rd 4 th 5 th frequency foldback mode vlo mode vlo mode f sw vs. p out , when p out is f sw vs. p out , when p out figure 30. typical switching frequency vs. output power relationship in a 10-w adapter 2.5 10 4 5.0 10 4 7.5 10 4 1.0 10 5 when an ?n? valley is asserted by the valley selection circuitry, the controller locks in this valley until the fb voltage decreases to the lower threshold (?n+1? valley activates) or increases to the ?n valley threshold? + 600 mv (?n ? 1? valley activates). the regulation loop adjusts the peak current to deliver the necessary output power at the valley operating point. each valley selection comparator features a 600 ? mv hysteresis that helps stabilize operation despite the fb voltage swing produced by the regulation loop. table 5. valley fb threshold on constant voltage regulation fb falling fb rising 1 st to 2 nd valley 2.5 v ff mode to 4 th 2.5 v 2 nd to 3 rd valley 2.3 v 4 th to 3 rd valley 2.7 v 3 rd to 4 th valley 2.1 v 3 rd to 2 nd valley 2.9 v 4 th to ff mode 1.9 v 2 nd to 1 st valley 3.1 v frequency foldback (ff) as the output current decreases (fb voltage decreases), the valleys are incremented from 1 to 4. in case the fourth valley is reached, the fb voltage further decreases below 1.9 v and the controller enters the frequency foldback mode (ff). the current setpoint being internally forced to remain above v cs(vco) (setpoint corresponding to v comp ), the controller regulates the power delivery by modulating the switching frequency. when an output current increase causes fb to exceed the 2.5 ? v ff upper threshold (600 ? mv hysteresis), the circuit recovers vlo operation. in frequency foldback mode, the system reduces the switching frequency by adding some dead ? time after the 4 th valley is detected. however, in order to keep the high efficiency benefit inherent to the qr operation, the controller turns on again with the next valley after the dead time has ended. as a result, the controller will still run in valley switching mode even when the ff is enabled. this dead ? time increases when the fb voltage decays. there is no discontinuity when the system transitions from vlo to ff and the frequency smoothly reduces as fb goes below 1.9 v. the dead ? time is selected to generate a 1.15 ? s dead ? time when v comp is decreasing and crossing v hvcod (1.9 v typ.). at this moment, it can linearly go down to the minimal frequency limit. the generated dead ? time is 650 ns when v comp is increasing and crossing v hvcoi (2.5 v typ.).
ncp11367 www. onsemi.com 20 v comp 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1 st valley 2 nd valley vco pout decreasing pout increasing 4.3 v 3 rd valley 4 th valley max peak current clamped to v cs = v ilim operating mode figure 31. valley lockout threshold stand ? by mode an high frozen peak current is necessary to have good efficiency at 10% of the load. on the other hand, the standby performance will not be optimized. indeed, in no load condition, the switching frequency has to be high enough to have a good transient response and then keep the output voltage within the limits. if we set a minimum switching frequency, the only parameter that can be ajusted to deliver less power is the primary peak current as shown in (eq. 16) . p out 1 2 i p,pk 2 f sw (eq. 16) the ncp11367 implements a peak control mode when the load is closed to 0. from frozen peak current in ff mode (250 mv here), the maximum voltage threshold on cs pin is reduced to 65 mv when the comp voltage crossed 260 v. if the 65 ? mv threshold is reached in 200 ns for instance due to small primary inductance, the minimum on time will be defined by the 320 ? ns leading edge blanking duration and the propagation delay (50 ns) so 370 ns typically. figure 32. frequency foldback and stanby mode behavior with 1-khz minimum frequency clamp, v cs(vco) = 250 mv and v cs(stb) = 65 mv
ncp11367 www. onsemi.com 21 current setpoint as explained in this operating description, the current setpoint is affected by several functions. figure 33 summarizes these interactions. as shown by this figure, the current setpoint is the output of the control law divided by k comp (4 typ.). this current setpoint is clamped by the soft ? start slope as long as the peak current requested by the fb_cv or fb_cc level are higher. the softstart clamp is starting from the frozen peak current ( v cs(vco) ) to v ilim (0.8 v typ.) within 4 ms ( t ss ). however, this internal fb value is also limited by the following functions: ? a minimum setpoint is forced that equals v cs ( vco ) (250 mv, typ.) when 0.760 v < v comp < 1.9 v ? a second minimum setpoint is forced that equals v cs (stb) (65 mv, typ.) when v comp < 0.260 v ? the peak current is linearly reduced between this two previous frozen peak current (v cs(vco) & v cs(stb) ) ? in addition, a second ocp comparator ensures that in any case the current setpoint is limited to v ilim . this ensures the mosfet current setpoint remains limited to v ilim in a fault condition. figure 33. current setpoint fb reset max_ipk reset ocp timer count reset timer leb1 cs v ilim poreset dblehiccup leb2 v cs(stop) 4 clk counter reset counter ocp 1/k comp scp control law for primary peak current control softstart fb_cv fb_cc pwm latch reset pwm comp ocp comp short circuit comp r sense r cs c cs peak current control comp a 2 nd over ? current comparator for abnormal overcurrent fault detection a severe fault like a winding short ? circuit can cause the switch current to increase very rapidly during the on ? time. the current sense signal significantly exceeds v ilim . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the power switch current can abnormally increase, possibly causing system damages. the ncp11367 protects against this dangerous mode by adding an additional comparator for abnormal overcurrent fault detection or short ? circuit condition. the current sense signal is blanked with a shorter leb duration, t leb2 , typically 120 ns, before applying it to the short ? circuit comparator. the voltage threshold of this extra comparator, v cs(stop) , is typically 1.2 v, set 50% higher than v ilim . this is to avoid interference with normal operation. four consecutive abnormal overcurrent faults cause the controller to enter in auto ? recovery mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the fault overcurrent comparator or after double hiccup sequence or if the power supply is unplugged with a new startup sequence after the initial power on reset. jittering capability in order to help meet the emi requirements, the ncp11367 features the jittering capability to average the spectrum rays over the frequency range. the function consists of adding a voltage ripple to the peak current information in order to change the operation frequency. the peak ? to ? peak amplitude of the ripple vaweform is 60 mv at 1.5 khz.
ncp11367 www. onsemi.com 22 v dd v jitter cs r lff r sense to cs comparator v cs time f jitter v jitter figure 34. frequency jittering fault mode and protection ? cs pin: at each startup, a 60 ? a ( i cs ) current source pulls up the cs pin to disable the controller if the pin is left open or grounded. then the controller enters in a double hiccup mode. ? vs/zcd pin: after sending the first drive pulse the controller checks the correct wiring of vs/zcd pin: after the zcd blanking time, if there is an open or short conditions, the controller enters in double hiccup mode. line feed forward the primary peak current slope is directly linked to the input voltage so measuring this slope via cs pin allows to generate a current to cs pin directly proportional to the slope in order to compensate the over current on cs pin due to the propagation delay. the resistor in series with the cs pin adjusts the compensation level. k lff *s sense r sense v dd cs r lff figure 35. internal line feed forward configuration the line feed forward compensation can be divided in two steps: 1. from drv rising to 1.1 s later, the controller measured the slope on the cs pin. during this time, no current flowing out the cs pin 2. after 1.1 s, a current flowing out the cs pin according to the slope to generate an offset on r lff resistance. please note that, at the end of the on time, the offset is removed until the next cycle. also, if the on time duration is closed to 1.1 s or lower, the lff function will not have any effects on the output current regulation. calculation of the resistor (r lff ) for compensating the overpower: the on time primary peak current slope seen on the cs pin is linked to the input voltage, primary inductance and the sense resistance: s sense v in l p r sense (eq. 17) in our flyback design, let?s assume that our primary inductance l p is 1.2 mh with 0.907 ? sense resistance. the slope at high line (265 v rms) will be: s sense(265) 265 2 1.2m 0.907 283mv s (eq. 18) knowing the line feed forward gain (k lff ), the lff current at high line will be: i lff(265) k lff s sense(265) 300 283m 85 a (eq. 19) let?s assume the power supply needs to have a compensation of 100 mv (v lff ) at 265 v rms (v in ), the resistor value to be inserted between the cs resistor and cs pin could be calculated, as illustrated here after: r lff v lff i lff(265) 100m 85 1.18 k (eq. 20) please note that lff current flowing out the cs pin will be also present at low line. the sense resistance will maybe have to be adjusted to set the right output current.
ncp11367 www. onsemi.com 23 thermal shutdown an internal thermal shutdown circuit monitors the junction temperature of controller die of the ic. the controller is disabled if its junction temperature exceeds the thermal shutdown threshold ( t shdn ). a continuous v cc hiccup is initiated after a thermal shutdown fault is detected. the controller restarts at the next v cc ( on ) once the ic temperature drops below t shdn reduced by the thermal shutdown hysteresis ( t shdn (off) ) . the thermal shutdown is also cleared if v cc drops below v cc ( reset ) . a new power up sequences commences at the next v cc ( on ) once all the faults are removed. table 6. ordering table option opn # ncp11367_ _ minimum switching frequency in vco mode (khz) maximum switching frequency (khz) cable drop compensation (mv) uvp blanking time (ms) a b a b c d a b c d g h a b c d 0.2 1 no 80 110 140 no 200 mv 12 v out 250 mv 12 v out 300 mv 12 v out 150 mv 5 v out 410 mv 12 v out 36 76 31 6 63 6 ncp11367bbab ydbr2g x x x x ncp11367bbbb ydbr2g x x x x ncp11367bbdb ydbr2g x x x x table 7. ordering information device marking package shipping ? NCP11367BBABYDBR2G 11367aaa tssop20 (pb ? free) tbd / tape & reel ncp11367bbbbydbr2g 11367aab tssop20 (pb ? free) tbd / tape & reel ncp11367bbdbydbr2g 11367aac tssop20 (pb ? free) tbd / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp11367 www. onsemi.com 24 package dimensions case 948bl issue o dim d min max 6.60 millimeters e1 4.30 4.50 a 1.10 a1 0.00 0.15 l 0.46 0.76 e 0.65 bsc c 0.09 0.20 b 0.19 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 max at mmc. dambar cannot be located on the lower ra- dius or the foot. minimum space between protrusion and lead is 0.07. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension d is determined at datum h. 5. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimension e1 is determined at datum h. 6. datums a and b are determined at datum h. 7. a1 is defined as the vertical distance from the seat- ing plane to the lowest point on the package body. 8. leads 7, 8, 13, 14, 18, and 19 are missing. pin 1 reference d e1 0.10 a seating plane 13x b e detail a 6.40 --- 13x 1.15 13x 0.42 0.65 dimensions: millimeters pitch soldering footprint l l2 gauge detail a a2 0.85 0.95 e 6.40 bsc plane seating plane c m end view b m 0.10 a c top view side view b 0.20 a c 110 11 20 b a 2x a2 c 0.05 c c 6.70 20x recommended l1 1.00 ref note 6 note 5 note 6 note 3 e a1 l1 note 7 h c note 4 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of on semiconductor ?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular pu rpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulatio ns and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semicond uctor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typicals? mus t be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconduc tor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or si milar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, cost s, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer . this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp11367/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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